The invention relates to the field of metal-oxide-semiconductor memory devices and, more particularly, to an improved substrate bias generator for random access memories.
A negative bias voltage is typically applied by a back bias generator to the substrate of a metal-oxide-semiconductor (MOS) random access memory (RAM) in order to improve the performance of the MOS circuit. The applied negative voltage, generally about minus 3.5 volts with respect to ground, lowers the junction capacitance between N+ doped silicon layers and the P- doped silicon substrate. As a result, the MOS circuit operates at a faster speed.
In addition to attaining faster circuitry speed, the application of back bias voltage to the substrate reduces the sensitivity of the threshold voltage in the memory chip to variations in the potential between the source of an MOS transistor and the substrate bias.
In previous generations of memory devices, the back bias voltage was developed externally to the memory chip. More recently, back bias voltages have been generated on the chips themselves by using a charge pump to develop a negative back bias voltage. However, the charge pumps are limited to pulling the substrate potential down to a voltage in the range of minus 2.5 to minus 3.5 volts due to threshold voltage drops associated with the pump.